Welcome to IEEE TCCA Email-Monthly, Oct. 2002: 1. Computer Architecture Letters submitted by: Kevin Skadron New papers published by Computer Architecture Letters 2. Six Workshops to be Held in conjunction with HPCA 9 - CAECW-02: Computer Architecture Evaluation Using Commercial Workloads - PACS'02: Power-Aware Computer Syste - Workshop on Network Processors: - NSC-1: Workshop on Non-Silicon Computing - SAN-1: Workshop on Novel Uses of System Area Network - INTERACT-6: Interaction between Compilers and Computer Architecture See http://www.hpcaconf.org/ for details 3. CAC '03: Workshop on Communication Architecture for Clusters submitted by Nectarios Koziris Call For Papers http://www.cis.ohio-state.edu/~cac 4. GLSVLSI 2003: The 2003 Great Lakes Symposium on VLSI submitted by John Lach CALL FOR PAPERS http://www.glsvlsi.org/ 5. INTERACT-7: The 7th IEEE Workshop on Interaction between Compilers and Computer Architectures submitted by Gyungho Lee Call-for-papers * Archive: http://www.ele.uri.edu/tcca * To submit an email message to be distributed among TCCA members, send an email to qyang@ele.uri.edu * To subscribe to this mailing list, please sign up at * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe ----------------------------------------------------------------------- Qing (Ken) Yang, Professor Distinguished Engineering Professor e-mail: qyang@ele.uri.edu Dept. of Electr. & Comput. Engineering Tel. (401) 874-5880 University of Rhode Island Fax (401) 782-6422 Kingston RI. 02881 http://www.ele.uri.edu/~qyang ------------------------------------------------------------------------ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~Message Details~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ New papers published by Computer Architecture Letters ----------------------------------------------------- To provide the fastest possible online publication, Computer Architecture Letters continues to announce newly accepted papers in this monthly e-mail to the SIGARCH and TCCA memberships. These papers can be obtained from our website, http://comp-arch-letters.org - S. Tambat, S. Vajapeyam. "Page-Level Behavior of Cache Contention." Volume 1, Jul. 2002. - P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi, D. W. Clark. "Implementing Decay Techniques using 4T Quasi-Static Memory Cells." Volume 1, Sep. 2002. "Letters" is a quarterly forum for fast publication of new, high-quality ideas in the form of short, critically refereed, technical papers. Accepted letters are published immediately on our website and in the next available paper issue. Submissions are accepted on a continuing basis. Current turn-around time is 33 days, and we hope to improve this as our review process becomes more efficient. Current acceptance rate is 20%. The kind of paper that we are seeking is an early, "wow" idea that may not yet be ready for a full conference publication, but has enough validated insights to justify publication as a four-page letter. Abstracts --------- - S. Tambat, S. Vajapeyam. "Page-Level Behavior of Cache Contention." Volume 1, Jul. 2002. Cache misses in small, limited -associativity primary caches very often replace live cache blocks, given the dominance of capacity and conflict misses. Towards motivating novel cache organizations, we study the comparative characteristics of the virtual memory address pairs involved in typical primary -cache contention (block replacements) for the SPEC2000 integer benchmarks. We focus on the cache tag bits, and results show that (i) often just a few tag bits differ between contending addresses, and (ii) accesses to certain segments or page groups of the virtual address space (i.e. certain tag-bit groups) contend frequently. Cacheconscious virtual address space allocation can further reduce the number of confl icting tag bits. We mention two directions for exploiting such page -level contention patterns to improve cache cost and performance. - P. Juang, P. Diodato, S. Kaxiras, K. Skadron, Z. Hu, M. Martonosi, D. W. Clark. "Implementing Decay Techniques using 4T Quasi-Static Memory Cells." Volume 1, Sep. 2002. This paper proposes the use of four-transistor (4T) cache and branch predictor array cell designs to address increasing worries regarding leakage power dissipation. While 4T designs lose state when infrequently accessed, they have very low leakage, smaller area, and no capacitive loads to switch. This short paper gives an overview of 4T implementation issues and a preliminary evaluation of leakage-energy savings that shows improvements of 60-80\%. -------------------------------------------------------------------------- Call For Papers Workshop on Communication Architecture for Clusters (CAC '03) To be held in Conjunction with Int'l Parallel and Distributed Processing Symposium (IPDPS '03) Nice Acropolis Convention Center, Nice, France April 22-26, 2003 ------------------------------------------------------------------------ - Postscript and PDF versions of this CFP may be obtained from the World Wide Web: http://www.cis.ohio-state.edu/~cac ------------------------------------------------------------------------ - THEME: The availability of commodity PCs/workstations and high-speed networks (Local Area Networks and System Area Networks) at low prices enabled the development of low-cost clusters. These clusters are being targeted for support of traditional high-end computing applications as well as emerging applications, especially those requiring high-performance servers. Designing high-performance and scalable clusters for these emerging applications requires design and development of high-performance communication and I/O subsystems, low-overhead programming environment support and support for Quality of Service (QoS). New user-level communication protocol standards such as Virtual Interface Architecture (VIA) and InfiniBand Architecture (IBA) are providing exciting ways to design high-performance communication and I/O architectures for clusters. A large number of research groups from academia, industry, and research labs are currently engaged in the above research directions. The goal of this workshop is to bring together researchers and practitioners working in the areas of communication, I/O, and architecture to discuss state-of-the-art solutions as well as future trends for designing scalable, high-performance, and cost-effective communication and I/O architectures for clusters. The first two workshops in this series (CAC '01 and CAC '02) were held in conjunction with IPDPS conferences, and they were very successful. The CAC '03 workshop plans to continue this tradition. TOPICS OF INTEREST: Topics of interest for the workshop include but are not limited to: 1. Router/switch, network, and network-interface architecture for supporting efficient point-to-point communication, collective communication, and I/O at intra-cluster and inter-cluster levels. 2. Design, development, and implementation of communication protocols (GM, VIA, TCP/IP, etc) on different networking and interconnect technologies (such as Myrinet, Gigabit Ethernet, InfiniBand, Quadrics, TCP Offload Engine, etc.). 3. High-performance implementation of different programming layers (Message Passing Interface (MPI), Distributed Shared Memory such as TreadMarks, Get/Put, Global Arrays, sockets, etc.) and File Systems (such as PVFS and DAFS). 4. Communication and architectural issues related to switch organization, flow control, congestion control, routing and deadlock-handling, load balancing, reliability, and QoS support. 5. Strategies, algorithms, and protocols for management of communication resources, including topology discovery, hot update/replacement of components, dynamic reconfigurations, etc. 6. Performance evaluation and tools for different application areas, including interprocessor communication and I/O, etc. Results of both theoretical and practical significance will be considered. PROCEEDINGS: The proceedings of this workshop will be published together with the proceedings of other IPDPS '03 workshops by the IEEE Computer Society Press. PAPER SUBMISSIONS: We are planning a purely electronic submission and review process. Authors are requested to submit papers (in PDF format) not exceeding 10 single-spaced pages, including abstract, five key words, contact address, figures, and references. E-mail your manuscripts to: cac@cis.ohio-state.edu. Note: the PDF file must be viewable using the ``acroread'' tool. It is also important, when creating your PDF file, to use a page size of 8.5x11 inches (LETTER sized output not A4), since an A4 sized page may be truncated on a LETTER sized printer. SCHEDULE: Paper submission: November 4, 2002 Notification of acceptance: December 16, 2002 Camera-ready due: January 24, 2003 WORKSHOP CO-CHAIRS: Dhabaleswar K. Panda (Ohio State), Jose Duato (Univ. of Valencia, Spain), and Craig Stunkel (IBM TJ Watson Research Center) PROGRAM COMMITTEE: Bulent Abali (IBM TJ Watson) Mohammad Banikazemi (IBM TJ Watson) Angelos Bilas (Univ. of Toronto, Canada) Alan Benner (IBM) Ron Brightwell (Sandia National Lab) Toni Cortes (UPC, Spain) Wu-Chun Feng (Los Alamos National Lab) Jose Manuel Garcia (Univ. of Murcia, Spain) Mitchell Gusat (IBM, Zurich) Mark Heinrich (Cornell Univ.) Manolis G.H. Katevenis (FORTH and Univ. of Crete, Greece) Nectarios G. Koziris (National Technical Univ. of Athens, Greece) Mario Lauria (Ohio State) Olav Lysne (Univ. of Oslo, Norway) Arthur (Barney) Mccabe (Univ. of New Mexico) Pankaj Mehra (HP) Shubu Mukherjee (Intel) Jarek Nieplocha (Pacific Northwest National Lab) Scott Pakin (Los Alamos National Lab) Fabrizio Petrini (Los Alamos National Lab) Greg Pfister (IBM) Timothy Pinkston (Univ. of Southern California) Antonio Robles (UPV, Spain) Tom Rokicki (Instantis) Reza Rooholamini (Dell) Hemal Shah (Intel) Anthony Skjellum (Mississippi State) Pete Wyckoff (Ohio Supercomputer Center) Xiaodong Zhang (NSF) PUBLICITY COORDINATORS: Darius Buntinas (Ohio State University) Nectarios G. Koziris (National Technical Univ. of Athens, Greece) ADDITIONAL INFORMATION: On the World Wide Web, see http://www.cis.ohio-state.edu/~cac for the latest information about this workshop. Alternatively, you can send e-mail to cac@cis.ohio-state.edu. ------------------------------------------- CALL FOR PAPERS GLSVLSI 2003 Washington D.C. April 28-29, 2003 http://www.glsvlsi.org/ OVERVIEW The 2003 Great Lakes Symposium on VLSI (GLSVLSI) will be held in Washington D.C. Original, unpublished papers, describing research in the general area of VLSI are solicited. Both theoretical and experimental research results are welcome. Proceedings will be published by the ACM and will be included on the SIGDA compendium CD-ROM. TOPICS The theme of this year's symposium is "VLSI in the Nanometer Era." Additional topics of interest include, but are not limited to: -VLSI Design: design of ASICs, microprocessors and micro-architectures, embedded processors, analog/digital/mixed-signal systems, multi-chip modules, FPGAs, PLDs. -VLSI Circuits: analog/digital/mixed-signal circuits, RF and communication circuits, chaos/neural/fuzzy-logic circuits, high-speed/low-power circuits. -Computer-Aided Design (CAD): hardware/software co-design, logic and behavioral synthesis, logic mapping, simulation and formal verification, layout (partitioning, placement, routing, floorplanning, compaction, etc.), algorithms and complexity analysis. -Low Power Design: circuits, micro-architectural techniques, CAD support, power estimation methodologies and tools. -Testing, Reliability, Fault-Tolerance: digital/analog/mixed-signal testing, design for testability and reliability, online testing techniques, static and dynamic defect- and fault-recoverability. -Nanotechnology: emerging technologies (resonant tunneling devices, single electron transistors, quantum devices, molecular electronics, etc.), circuit design using nanotechnology devices, modeling and simulation tools for nanoelectronic devices and circuits. IMPORTANT DATES Submission deadline: January 10, 2003 (5:00pm EST) Acceptance notification: February 14, 2003 Camera ready paper due: March 7, 2003 PAPER SUBMISSION Authors are invited to submit full-length (6 pages maximum), original, unpublished papers along with an abstract of at most 200 words. To enable blind review, author and contact information (name, street/mailing address, telephone, fax, e-mail) should be submitted in a separate document. Previously published papers or papers submitted for publication to other conferences/journals will not be considered. Electronic submission to the website is required. PAPER FORMAT To allow reduced turn-around time for accepted papers, GLSVLSI 2003 submissions should be in camera-ready two-column format, following the ACM proceedings specifications located at: http://www.acm.org/sigs/pubs/proceed/template.html SYMPOSIUM PRESENTATIONS Papers will be accepted for long, short, or poster presentation at the symposium. BEST PAPER AWARD A "Best Paper Award" will be voted on by the technical program committee and will be awarded during the symposium's opening session. SPONSORSHIP AND TECHNICAL SUPPORT The 2003 GLSVLSI is sponsored by ACM SIGDA, and technical support is provided by IEEE CAS. -------------------------------------------------------------------------- ================== (INTERACT-7 Call-for-Papers) =============== INTERACT-7 (The 7th IEEE Workshop on Interaction between Compilers and Computer Architectures) will be held again in conjunction with the HPCA in Feb., 2003. We'd like to invite your participation: submission of your contribution is due by Nov. 30, 2002. As in the last year, post workshop proceedings will be published by the IEEE Computer Society Press. For details, please visit INTERACT web site: http://api.ece.uic.edu/~Interact7/index.html Wei-Chung Hsu Gyungho Lee Associate Professor, Dept. CS Professor, Dept. ECE University of Minnesota University of Illinois at Chicago Email: hsu@cs.umn.edu email: ghlee@ece.uic.edu Phoen: (612) 625-2013 phone: 312-413-9657 -------------------------------------------------------------------------- * To unsubscribe yourself from this mailing list: email to tcca-request@ele.uri.edu with message body: unsubscribe